1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure isolating elements from each other by an isolation film such as a partial insulator film partially leaving an SOI layer and a method of manufacturing the same.
2. Description of the Background Art
For example, each of “Y. Hirano et al., IEEE 1999 SOI conf., p 131” (Reference 1), Japanese Patent Application Laid-Open No. 2000-243973 (U.S. patent application Ser. No. 09/466,934: Reference 2) and Japanese Patent Application No. 2000-39484 (U.S. patent application Ser. No. 09/639,953: Reference 3) discloses a semiconductor device having a conventional SOI structure (may hereinafter be referred to as “partially isolated body fixed SOI structure”) isolating elements from each other by an isolation film such as a partial insulator film partially leaving an SOI layer and fixing the potential of a body region.
In such a semiconductor device having a partially isolated body fixed SOI structure, however, it is difficult to form a semiconductor element such as a MOSFET while precisely controlling body resistance. The reason therefor is now described in detail.
FIG. 33 is a sectional view for illustrating a problem of the conventional partially isolated body fixed SOI structure. As shown in FIG. 33, an SOI layer 3 is formed on an embedded oxide film 2 present on a silicon substrate (not shown), and subjected to element isolation by a partial oxide film 31. The partial oxide film 31 is formed to leave a well region 11, which is a lower part of the SOI layer 3, under the same.
A channel forming region 7 is formed in a transistor forming region of the SOI layer 3, so that a gate oxide film 8 and a gate electrode 9 are successively formed on the channel forming region 7.
On the other hand, a body region 10 is provided oppositely to the channel forming region 7 through the partial oxide film 31, and this body region 10 is electrically connected with the channel forming region 7 through the well region 11 located under the partial oxide film 31 since the well region 11 is in contact with the body region 10 and the channel forming region 7 respectively.
In order to form a source/drain region of a MOS transistor, S/D impurity ions 19 are implanted through the gate electrode 9 etc. serving as masks as shown in FIG. 33, while no mask is provided (no resist film is formed) on the partial oxide film 31 in general.
When forming the source/drain region, therefore, the S/D impurity ions 19 may be partially implanted into the well region 11 located under the partial oxide film 31 to increase the resistance value of body resistance, which is the resistance of the well region 11 reaching the channel forming region 7 from the body region 10, disadvantageously resulting in unstable high-speed operation of the MOS transistor.
As the S/D impurity ions 19 for forming the source/drain region, As (arsenic) ions are implanted under conditions of 50 keV (injection energy) and 4×1015/cm2 (dose), for example.
FIG. 34 is a graph showing the impurity profile of As implanted under the aforementioned conditions. As shown in FIG. 34, the impurity profile has standard deviation σ (=8.5 nm) with reference to 26 nm, reaching a range of 51.5 nm (=26+3σ (nm)).
When the thickness of the partial oxide film 31 is reduced to about 50 nm, therefore, the impurity ions 19 of As disadvantageously reach the well region 11. Also when the thickness of the partial oxide film 31 is slightly larger than 50 nm, the As ions may still be implanted into the partial oxide film 31 since the tail part of the impurity profile is deeper than 51.5 nm.
In order to reduce a leakage current from a silicide region of CoSi2 (cobalt silicide) or the like, P (phosphorus) is implanted under conditions of about 30 to 50 keV and about 1×1013/cm2. However, P has a higher possibility of reaching the well region 11 than As, due to a range deeper than that of As.
When trench isolation is employed, the partial oxide film 31 is formed by CMP (chemical mechanical polishing). Therefore, the thickness of the partial oxide film 31 is remarkably dispersed by about ±30 nm, for example, depending on pattern density or the position in a wafer surface.
Therefore, the partial oxide film 31 must be formed while setting a margin in consideration of the aforementioned dispersion. When the thickness of the partial oxide film 31 is so set that the As ions 19 for forming the source/drain region are not implanted into the well region 11 located under the partial oxide film 31, however, an isolation step 32 between the surface of the SOI layer 3, which is the surface of the SOI substrate, and the surface of the partial oxide film 31 reaches an unignorable level, as shown in FIG. 35.
Consequently, a residue 33 may be left on a side surface of the partial oxide film 31 as shown in FIG. 35. If an etching time for gate formation is increased for preventing formation of the residue 33, the gate oxide film 8 is disadvantageously damaged and reduced in reliability.
FIG. 36 is a plan view of a semiconductor device having the conventional partially separated body fixed SOI structure. FIG. 33 is a sectional view taken along the line C—C in FIG. 36. When an N-type impurity is implanted for forming the source/drain region, an N+ block region 40 covering the overall body region 10 is masked with a resist film or the like, so that the N-type impurity is not implanted into the P-type body region 10.
As shown in FIG. 36, the N+ block region 40 is generally formed in the minimum necessary size for reliably covering the body region 10, so that the gate oxide film 8 is not charged and statically damaged by a charge-up phenomenon.
When a P-type impurity is implanted into the body region 10, on the other hand, a P+ block region 39 entirely covering an N-type drain region 5 and an N-type source region 6 is masked with a resist film or the like, so that the P-type impurity is not implanted into the drain region 5 and the source region 6.
As shown in FIG. 36, further, the P+ block region 39 is generally formed in the minimum necessary size for reliably covering the drain region 5 and the source region 6, for a reason similar to that for the N+ block region 40.
As hereinabove described, the source/drain region and the body region 10 are formed while masking the N+ block region 40 and the P+ block region 39 respectively, and hence it follows that both of the N- and P-type impurities are implanted into regions other than the N+ block region 40 and the P+ block region 39.
Consequently, the impurities are implanted into the well region 11 electrically connecting the body region 10 with the channel forming region 7 (not illustrated in FIG. 36 but present in the SOI layer 3 located under the gate electrode 9 as shown in FIG. 33), to cause such inconvenience that the resistance value of the body resistance R1 of the well region 11 reaching the channel forming region 7 from the body region 10 is increased or dispersed. Thus, it is difficult to precisely control the body resistance R1.
When the resistance value of the body resistance R1 is increased, the threshold voltage of the transistor fluctuates to disadvantageously resulting in unstable operation. This problem is disclosed in “S. Maeda et al., IEEE Transaction on Electron Devices, vol. 45, No. 7, pp. 1479 to 1486 (1998)”, for example.
The body resistance serves as a noise source increasing noise of the transistor. When a circuit such as a PLL (phase locked loop) circuit is formed by a transistor having unstable body resistance, therefore, phase noise (phase jitter) is disadvantageously increased.
Thus, it is important for a semiconductor device having a partially isolated body fixed SOI structure to reduce and stably control body resistance.